1. Field of the Invention
The present invention relates to a technique for driving a liquid crystal panel of a liquid crystal display (LCD) and, more particularly, to a driving circuit of an LCD capable of preventing degradation of characteristics of transistors constituting a gate driving unit, an element of a gate driving unit.
2. Description of the Related Art
Recently, as the information technology (IT) is advancing, the importance of a flat panel display device is further emphasized as a visual information transmission medium, and in order to obtain a competitive edge in the future, the flat panel display device is required to have low power consumption, to be thinner and lighter, and to have high picture quality. A liquid crystal display (LCD), a typical display device of the flat panel display devices, displays an image by using optical anisotropy of liquid crystal. With the advantages of being thinner and smaller and having low power consumption and high picture quality, the LCD is widely applied for display devices of various mobile terminals such as a TV receiver or the like.
The LCD is a display device in which image information is individually supplied to liquid crystal pixels arranged in a matrix form to control light transmittance of the liquid crystal pixels to thereby display a desired image. Thus, the LCD includes a liquid crystal panel with liquid crystal pixels, the minimum unit for implementing an image, arranged in a matrix form and a driver for driving the liquid crystal panel. Because the LCD does not emit light by itself, it includes a backlight unit to provide light to the LCD. The driver includes a data driving unit and a gate driving unit as well as a timing controller.
FIG. 1 is a block diagram of a related art LCD. As shown in FIG. 1, the related art LCD includes a timing controller 14 that outputs a gate control signal GDC and a data control signal DDC for controlling driving of a gate driving unit 12 and a data driving unit 13, samples digital video data RGB, realigns them, and outputs the same; the gate driving unit 12 that supplies gate signals to gate lines GL0˜GLn of a liquid crystal panel 14 in response to the gate control signal GDC; a data driving unit 13 that supplies pixel signals to data lines DL1˜DLm of the liquid crystal panel 14 in response to the data control signal DDC; and the liquid crystal panel 14 including liquid crystal cells arranged in a matrix form and driven by the gate signals and the pixel signals to display an image. The operation of the LCD will now be described with reference to FIGS. 2 to 7.
The timing controller 11 outputs the gate control signal GDC for controlling the gate driving unit 12 and the data control signal DDC for controlling the data driving unit 13 by using a vertical/horizontal synchronization signals (Hsync/Vsync) supplied from a system. Also, the timing controller 11 samples digital pixel data RGB inputted from the system, realigns the same and supplies it to the data driving unit 13.
The gate control signal GDC includes a gate start pulse GSP, a gate shift clock signal GSC, a gate out enable signal GOE, or the like, and the data control signal DDC includes a source start pulse SSP, a source shift clock signal SSC, a source out enable signal SOE, and a polarity signal POL.
The gate driving unit 12 sequentially supplies gate signals to the gate lines GL1˜GLn in response to the gate control signal GDC inputted from the timing controller 11, and accordingly, thin film transistors TFTs in the horizontal lines are turned on. Accordingly, pixel signals supplied via the data lines DL1˜DLm are stored in each storage capacitor Cst via the TFTs.
In detail, the gate driving unit 12 shifts the gate start pulse GSP according to the gate shift clock GSC to generate a shift pulse. The gate driving unit 12 supplies a gate signal including a gate-on and gate-off intervals (signals) to a corresponding gate line GL at every horizontal period in response to the shift clock. In this case, the gate driving unit supplies a gate-on signal only during an enable period in response to the gate out enable signal GOE, and supplies a gate-off signal during other period.
In response to the data control signal DDC inputted from the timing controller 11, the data driving unit 13 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to a gray scale value of the pixel data RGB, and supplies the converted pixel signal to the data lines DL1˜DLm on the liquid crystal panel 14.
The liquid crystal panel 14 includes a plurality of liquid crystal cells CLC arranged in a matrix form and TFTs formed at every crossing of the data lines DL1˜DLm and gate lines GL1˜GLn and connected to each liquid crystal cell CLC. When the gate signals are supplied from the gate lines GL, the TFTs are turned on to supply the pixel signals supplied via the data lines DL to the liquid crystal cells CLC. When the gate off signal is supplied through the gate lines GL, the TFTs are turned off to allow the pixel signal charged in the liquid crystal cell CLC to be maintained.
The liquid crystal cell CLC includes a common electrode and a pixel electrode connected with the TFTs with liquid crystals interposed therebetween. The liquid crystal cell CLC further includes a storage capacitor CST in order to stably maintain the charged pixel signal until a next pixel signal is charged. The storage capacitor CST is formed between the pixel electrode and a gate line of a previous stage. In the liquid crystal cell CLC, the arrangement of liquid crystals having dielectric anisotropy varies according to the pixel signal charged through the TFT, and accordingly, the light transmittance is adjusted to implement gray scales.
As shown in FIG. 2, the gate driving unit 12 includes gate drivers GD1˜GDn operating according to a shift register method, and outputs gate signals VGOUT[1]˜VGOUT[N] at the same timing as that shown in FIG. 3 by a clock signal CLK, a start signal VST and a reset signal RST supplied from the timing controller 11. Namely, after the start signal VST is inputted, the gate drivers GD1˜GDn sequentially output the gate signals VGOUT[1]˜VGOUT[N] in synchronization with corresponding clock signals CLK[1]˜CLK[N]. The gate lines GL1˜GLn on the liquid crystal panel 14 are driven by the thusly outputted gate signals VGOUT[1]˜VGOUT[N]. The operation of generating the gate signals VGOUT[1]˜VGOUT[N] is repeated by frames.
FIG. 4 is a detailed circuit diagram showing the gate drivers GD1˜GDn. A first AND gate AD11 ANDs control signals CTL supplied from the timing controller 11 and supplies a set signal (S) of an RS flipflop FF11, and a second AND gate AD12 ANDs the control signals CTL and supplies a reset signal (R) of the flip-flop FF11. The RS flipflop FF11 are operated by the supplied set signal (S) and the reset signal (R) to output the opposite logic signals as shown in FIG. 5 to its output terminals Q and QB.
In other words, when a gate high voltage VGH is outputted to the output terminal (Q) of the RS flipflop FF11, a large-size charging transistor TU is turned on, and at this time, a small-size discharging transistor TPD is turned off by a gate low voltage VGL outputted from the inversion output terminal QB of the RF flipflop FF11. In this state, when the clock signal CLK is supplied, the gate high voltage VGH is supplied to the corresponding gate line GL from the charging transistor TU.
Thereafter, in a discharge mode, the discharging transistor TPD is turned on by the gate high voltage VGH outputted from the inversion output terminal QB of the RS flipflop FF11. Accordingly, the gate high voltage VGH, charging voltage of the gate line GL, is discharged via the discharging transistor TPD and maintained as a gate low voltage VGL.
The charging transistor TPU and the discharging transistor TPD are implemented as an a-Si:H TFT. When a positive polarity DC voltage is supplied between a source electrode and a gate electrode in such a transistor, a threshold voltage is increased to degrade the characteristics to reduce an output current.
In this respect, as shown in FIG. 5, it is noted that a high level voltage is outputted from the output terminal (Q) of the RS flipflop FF11 to a gate electrode of the charging transistor TU during a short time corresponding to a charge time of the gate line. Thus, the charging transistor TU can receive a stress voltage during the short time period.
In comparison, it is noted that a high level voltage is outputted from the output terminal QB of the RF flipflop FF11 to a gate electrode of the discharging transistor TPD during a long time excluding the charge time of the gate line. Thus, the discharging transistor TPD receives the stress voltage during a relatively even longer time compared with that of the charging transistor TU.
Thus, in the related art LCD, when the gate driving unit outputs the gate signals to the respective gate lines of the liquid crystal panel, the high level gate voltage is supplied to the charging transistor during a short time period, so degradation of characteristics proceeds relatively slow. Meanwhile, the discharging transistor at each gate driving unit receives the gate voltage of high level during a longer time compared with that of the charging transistor, so degradation of characteristics proceeds fast as much. This results in lengthening of a discharge time of the gate lines, causing a problem in that an interval, which is to be maintained in an OFF state, is not turned off to output an abnormal voltage.
In addition, the charging transistor TU and the discharging transistor TD are implemented by a-Si:H, having a disadvantage that the charging transistor TPU and the discharging transistor TPD have low mobility. Thus, the related art LCD has the problem that gate lines are not discharged within a line time.